1. Field of the Invention
The present relates to semiconductor devices, and in particular methods and structures pertaining to shallow trench isolations (STIs)
2. Description of the Related Art
In semiconductor integrated circuits (ICs), millions of metal-oxide-semiconductors (MOS) transistors are formed on typical silicon substrates produced by Very Large Scale Integration (VLSI) processing methods. To create isolation and to assist in preventing short circuits between adjacent MOS transistors, an insulation structure between these MOS devices are formed. An oxide filled recessed oxide structure (ROX), or an oxide filled STI (shallow trench isolation) structure, is typically used for isolation. These structures are formed around the MOS device active regions. STI structures have been used for many years in the semiconductor industry to maintain isolation between devices, as well as between diffusion regions. STI structures have found favor because they create a near planar surface in the silicon substrate, which is useful for subsequent processing that involves photolithography, since planar structures provide a constant xe2x80x9cdepth of fieldxe2x80x9d for imaging.
Referring to FIG. 1A to FIG. 1D, a conventional method of fabricating an STI structure on a substrate 10 having an upper surface 12 is described. In FIG. 1A, a thin pad nitride 16 is first formed on upper surface 12, followed by a thin pad oxide layer 20, resulting in a combined layer 24. Using chemical vapor deposition (CVD), a silicon nitride layer 30 is formed on pad oxide layer 20. A photo-resist layer 34 is then formed and patterned on silicon nitride layer 30.
The photo-resist layer is applied, image exposed and developed to created an imaged photo-resist layer. This imaged photo-resist layer 34 is used as a mask over the silicon nitride layer 30, pad oxide layer 20, and substrate 10. This mask is used in conjunction with a directional etch to form a trench 40, as shown in FIG. 1B. Trench 40 penetrates partially into substrate 10.
With reference now to FIG. 1C, photo-resist layer 34 is removed. Trench 40 is then filled with an oxide layer 46 (e.g., silicon oxide layer) formed by atmospheric pressure CVD (APCVD) with tetra-ethyl-ortho-silicate (TEOS) as a gas source. In the case of a TEOS base oxide layer, a process of densification is performed after deposition at about 1000 degrees C. for 10 min to 30 min.
With reference now to FIG. 1D, using chemical-mechanical polishing (CMP), TEOS base silicon oxide layer 46 is removed, with silicon nitride layer 30 serving as a polish stop layer. This forms an oxide plug 50 within trench 40. Since oxide plug 50 is softer than silicon nitride layer 30, during CMP, a recess (not shown) is formed in the junction between oxide plug 50 and the silicon nitride layer 30.
With reference now to FIG. 1E, silicon nitride layer 30 is etched using a CF4+O2 isotropic plasma etch, which stops at the top of pad oxide 20 and does not etch oxide plug 50. This etch exposes combined layer 24.
In FIG. 1F, oxide plug 50 and pad oxide 20 are subject to chemical-mechanical polish (CMP). The polishing stops at the top of pad nitride layer 16. Pad nitride layer 16, which is very thin, can be removed by a wet etch strip. This is followed by a thermal oxidation and growth of a gate oxide. A MOS transistor is then formed using conventional methods.
Thermal annealing techniques are also used in semiconductor manufacturing for a variety of reasons, including activating dopants within a device. Thermal annealing processing involves heating a substrate (e.g., a silicon wafer). One type of heating or annealing used in VLSI processing is Laser Thermal Annealing (LTA). LTA is performed with laser light of a given wavelength, which is absorbed by the different regions of the substrate on which the device is formed, thereby heating these regions. Because of the different thermal and optical properties of the substrate to be processed, different regions of the substrate heat to different temperatures. For instance, a polysilicon gate electrode is optically different than an amorphized silicon region, which is once again optically different than an STI region. An STI region, filled with oxide, is essential transparent to the wavelength of light used in laser thermal annealing. Accordingly, the region of the substrate under the STI is heated since this region absorbs light. This can cause redistribution of dopant under the gate, or can liquify the silicon under the STI. This, in turn, can cause stress and hence dislocations in the silicon substrate, as well as possibly movement of the STI region.
Therefore, when performing LTA, it is important to be able to anneal certain regions on the substrate to a greater degree than others. It is thus necessary to be able to control the optical properties of the different regions of the substrate, independent of the physical or device requirements. of the regions. This would allows maximum flexibility in laser annealing processing, and provide a large degree of freedom with regard to the amount of laser energy able to be coupled to different regions of the semiconductor substrate. Unfortunately, the transparent nature of oxides used in forming STI structures has, to date, limited the control and successful application of laser thermal annealing because of the above-described adverse effects on the underlying substrate due to heating of the region beneath the STI structure.
The present invention relates to semiconductor devices, and in particular methods and structures pertaining to shallow trench isolations (STIs).
A first aspect of the invention is an STI structure (hereinafter, simply xe2x80x9cSTIxe2x80x9d) formed in a silicon substrate, capable of absorbing laser light, for use in sub-micron integrated circuit devices. The STI of the present invention provides reduced absorption of a wavelength of laser light during laser annealing, and comprises a shallow trench of 0.5 xcexcm or less etched in the silicon substrate. The reduced light absorption is obtained by the addition of an, optical blocking member comprising an insulator designed to reflect or absorb the wavelength of laser light, formed in the shallow trench. The optical blocking member is preferably between 100 and 500 angstroms thick and is designed to reflect or absorb a sufficient amount of the wavelength of laser light so as to mitigate diffusion of dopants and/or recrystallization of a portion of the silicon substrate. In a preferred embodiment, the optical blocking member comprises silicon nitride. The optical blocking member has a thickness that is equal to or less than the width of the trench.
A second aspect of the invention is a method of forming an STI. The STI is formed in a silicon substrate having an upper surface. The method comprises the steps of first, forming in the silicon substrate a trench having an inner surface and lower wall, then forming a first insulator layer within the trench conformal with the inner surface and the lower wall, and a second insulator layer within the trench conformal with the inner surface and the lower wall, the second insulating layer capable of reflecting or absorbing a wavelength of light used in laser annealing. The final step is then forming a third insulating layer atop the second insulating layer so as to fill the trench. The first insulating layer serves as an optical blocking member that reflects or absorbs the wavelength of light used in laser annealing so that the region of the substrate underneath the STI is not heated by absorption of the wavelength of light during laser-annealing.
A third aspect of the invention is another method of forming in a silicon substrate having an upper surface, a shallow trench isolation having an optical blocking member therein. The method comprises the steps of first, forming a trench having an inner surface and lower wall in the silicon substrate. The next step is forming a first insulator layer within the trench conformal with the inner surface and the lower wall. The next step is forming a second insulating layer atop the first insulating layer. This second insulating layer is capable of reflecting or absorbing a wavelength of light used in laser annealing. The final step is forming a third insulator layer atop the second insulating layer that fills the trench. The second insulating layer is removed from the lower wall of the trench by the first insulating layer, and serves as an optical blocking member that absorbs the wavelength of light used in laser annealing so that the region of the substrate underneath the STI is not heated by absorption of the wavelength. of light during laser annealing. The optical blocking member formed by this method can have a width equal to or less than the width of the trench. Thus, the width of the optical blocking member can be varied to control the amount of absorption of light within the STI.